The present invention relates to differential pair amplifiers, and in particular to a folded floating-gate differential pair.
Conventional MOS differential pairs are used as inputs to operational amplifiers, operational transconductance amplifiers (OTAs), mixers, and many other circuits. The differential pair convert a voltage difference into a current difference in a more or less linear fashion, independent of common-mode input voltage. FIG. 1 shows a prior art differential pair comprising a simple nMOS differential pair biased using a constant current source provided by a single saturated nMOS transistor. A nearly constant transconductance is maintained by keeping the sum of the two output currents, I1+I2, fixed at a constant value, Ib. The voltage on a common source node, V, moves up and down with the input voltages V1 and V2.
In order to maintain a constant transconductance from such a simple differential pair, the common-mode input voltage should stay sufficiently far above ground so that the gate-to-source voltage of the input transistors is large enough for them to pass a significant fraction of Ib and so that the transistor that sinks the bias current remains in saturation. For bias currents at or near threshold, the input common-mode voltage must remain greater than approximately VT0+Vsat. This restriction on the common-mode input voltage makes the simple differential pair unattractive for low-voltage (e.g., VDDxe2x89xa62 V) applications.
One method that has been proposed for overcoming this limitation of the simple differential pair in low-voltage applications is to construct the differential pair from floating-gate MOS (FGMOS) transistors, as shown in prior art FIG. 2. Charge stored on the gates of the FGMOS transistors are used as a level shift so that the common-mode control-gate input voltage can be at ground, while the common-mode floating-gate voltage is high enough to permit proper operation of the differential pair. However, this scheme actually reduces the output-voltage swing, because the common-source node will be higher than it would be in the conventional differential pair for any given common-mode input voltage.
A folded floating-gate MOS differential pair amplifier comprises a matched pair of transistors whose output currents are summed and compared with a constant bias current. The voltage at a comparison node is used to regulate the total output current via shunt feedback to the gates of each transistor in the pair. The swing of this voltage is folded up into the same range over which the input and output voltages swing. Output currents for the circuit are formed with a second set of matched transistors as mirror copies of those that are regulated. In a further embodiment, feedback that regulates the sum of the currents is provided to an extra control gate connected to the floating gates.
The control gate comprises a capacitor in one embodiment that is coupled to gates of the differential pair transistors and to those of the output transistors.